Semiconductor device and method for manufacturing the same

ABSTRACT

According to the present invention, there is provided a method for manufacturing a semiconductor device, including the steps of forming an insulating film on a silicon substrate, forming a first conductive film on the insulating film, forming an aluminum crystal layer on the first conductive film, forming a ferroelectric film containing Pb(ZrxTi1-x)O3 (where 0≰x≰1) on the aluminum crystal layer, forming a second conductive film on the ferroelectric film, and patterning the first conductive film, the ferroelectric film, and the second conductive film to form a capacitor including a lower electrode, a capacitor dielectric film, and an upper electrode which are laminated sequentially.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of prior International PatentApplication No. PCT/JP2005/015985 filed Sep. 1, 2005, the entirecontents of which are incorporated herein by reference.

TECHNICAL FIELD

It is related to a semiconductor device and a method for manufacturingthe semiconductor device.

BACKGROUND

Flash memories and ferroelectric memories are known as non-volatilememories capable of retaining stored information even after the power isturned off.

Among these, flash memory has a floating gate embedded in a gateinsulating film of an insulated-gate field-effect transistor (IGFET) tostore information by accumulating, in this floating gate, electriccharges indicating information. However, for such a flash memory, atunnel current needs to be applied to the gate insulating film at thetime of writing or deleting information. Thus, the flash memory isdisadvantageous in that a relatively high voltage is needed.

In contrast, the ferroelectric memory, which is also referred to asFeRAMs (Ferroelectric Random Access Memories), store information byutilizing hysteresis characteristics of a ferroelectric film formed in aferroelectric capacitor. The ferroelectric film is polarized inaccordance with a voltage applied between the upper and lower electrodesof the capacitor, and spontaneous polarization remains even after thevoltage is turned off. When polarity of an applied voltage is reversed,the spontaneous polarization is also reversed. Directions of thespontaneous polarization are associated with “1” and “0”, so thatinformation is written in the ferroelectric film. Thus, FeRAMs areadvantageous in that a voltage required for this writing is lower thanthat required in the case of flash memories, and that writing can becarried out at a higher speed than that in the case of flash memories.

FIG. 1 is a cross-sectional view of a capacitor Q of the FeRAM.

As shown in the figure, the capacitor Q is formed by stacking lowerelectrode 101, a capacitor dielectric film 102, and an upper electrode103 in this order on an underlying film 100.

Among these, for the capacitor dielectric film 102, a PZT (Pb(Zr_(x),Ti_(1-x))O₃) film is generally used. The ferroelectric characteristics,such as residual polarization charges, of the PZT film greatly depend onan orientation of PZT crystals. When the orientation of the PZT isaligned in (111) direction, its ferroelectric characteristic can beenhanced.

On the other hand, a stacked film including a titanium (Ti) film and aplatinum (Pt) film formed in this order is used for the lower electrode101. In this stacked film, titanium in the titanium film diffuses alongthe grain boundary of the platinum film, and then reaches a surface ofthe platinum film. When the PZT film is formed on the stacked film by asputtering method, the titanium is oxidized by a small amount of oxygencontained in the PZT to form a titanium oxide (TiO₂) nucleus. Thistitanium oxide serves as an initial growth nucleus of the PZT film, sothat the orientation of the PZT film is aligned in the (111) direction.

Note that, the titanium oxide nucleus can also be formed when the PZTfilm is crystallized by an anneal in an oxygen atmosphere.

In addition, since the lattice mismatch of Pt (111) and PZT (111) issmall, a PZT film with reduced defects due to the lattice mismatch canbe formed on the platinum film.

The capacitor dielectric film 102 used in such a capacitor Q is requiredto have high-density crystals so that high ferroelectricity can beobtained even when the capacitor Q is miniaturized. Thus, in order tomeet this requirement, a MOCVD (metal organic CVD) method is preferablyemployed as a method for forming the capacitor dielectric film 102,instead of a sol-gel method or a sputtering method.

However, if the PZT film is formed by the MOCVD method, lead (Pb) in thePZT film reacts with platinum in the lower electrode 101, and therebysurface roughness in the lower electrode 101 is caused. This surfaceroughness makes it difficult to align the orientation of the PZT film inthe (111) direction.

In another method, an oxide, such as an iridium oxide (IrO_(x)) film, isformed as the lower electrode 101, so that the PZT film is oriented inthe (111) direction by the effect of the orientation of the oxide.However, when a PZT film is formed by the MOCVD method on the lowerelectrode 101 made of an oxide, the oxide is reduced by PZT, whichresults in causing the lower electrode 101 to be amorphous. This makesimpossible to control the orientation of the PZT film by using theorientation of the lower electrode 101.

Accordingly, when the PZT film is formed by the MOCVD method, an iridium(Ir) film is often formed as the lower electrode 101. In this case, inorder to form titanium oxide which is to be an initial growth nucleus ofthe PZT on the lower electrode 101, a titanium film may be formed underthe iridium film to cause titanium to be diffused to the upper surfaceof the iridium film along the grain boundary of iridium.

However, since the iridium film has grains which are smaller and denserthan those of the platinum film, the diffusion of titanium along thegrain boundary of iridium cannot be expected, and thus theabove-described initial growth nucleus is not generated. Hence, if astacked film of an iridium film and a titanium film is used for thelower electrode 101, it is difficult to cause PZT to be oriented in the(111) direction by utilizing the initial growth nucleus of titaniumoxide.

Moreover, the lattice constant of Ir (111) is smaller than that of PZT(111), so that the lattice mismatch of the iridium film and the PZT filmis large. As a result, the PZT film formed on the iridium film isoriented in a direction different from a polarity direction (111), or israndomly oriented.

In the above description, the case of using titanium oxide as theinitial growth nucleus of PZT has been described. In the Patent document1 below, however, PbTiO₃ is used as the initial growth nucleus.

However, since PbTiO₃ is a ternary compound, it is difficult to controlits composition ratio.

Patent document 2 discloses that a titanium oxide film is formed on aniridium film to be a lower electrode, and then the titanium oxide filmis used as a nucleus to form a PZT film.

However, titanium oxide, such as TiO₂, can be in various bonding statesdepending on an oxidizing temperature or atmosphere. Thus, it isdifficult to control the orientation of titanium oxide.

In this manner, it has been extremely difficult to form, on an iridiumfilm, a PZT film with an orientation aligned in the (111) direction.

In addition to the above-described techniques, Patent documents 3 and 4also disclose techniques relating to the present application.

-   Patent document 1: Japanese Patent Laid Open 2000-58525-   Patent document 2: Japanese Patent Laid Open Hei 10-12832-   Patent document 3: Japanese Patent Laid Open Hei 9-282943-   Patent document 4: Japanese Patent Laid Open Hei 11-297966

SUMMARY

It is an aspect of the embodiments discussed herein to provide a methodfor manufacturing a semiconductor device, including, forming aninsulating film over a semiconductor substrate, forming a firstconductive film over the insulating film, forming an aluminum crystallayer on the first conductive film, forming a ferroelectric filmcontaining Pb(Zr_(x)Ti_(1-x))O₃ (where 0≦x≦1) on the aluminum crystallayer, forming a second conductive film on the ferroelectric film, andpatterning the first conductive film, the ferroelectric film, and thesecond conductive film to form a capacitor including a lower electrode,a capacitor dielectric film, an upper electrode which are sequentiallystacked.

These together with other aspects and advantages which will besubsequently apparent, reside in the details of construction andoperation as more fully hereinafter described and claimed, referencebeing had to the accompanying drawings forming a part hereof, whereinlike numerals refer to like parts throughout.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a capacitor provided in asemiconductor device according to a conventional technology;

FIGS. 2A to 2L are cross-sectional views showing processes ofmanufacturing a semiconductor device according to a first embodiment;

FIG. 3 is a graph obtained by investigating a lattice spacing differencein relation to the PZT (111) for various crystals;

FIGS. 4A to 4J are cross-sectional views showing processes ofmanufacturing a semiconductor device according to a second embodiment;

FIG. 5 is a cross-sectional view of the semiconductor device accordingto the first embodiment with a structure that two layers of capacitordielectric films are formed; and

FIG. 6 is a cross-sectional view of the semiconductor device accordingto the second embodiment with a structure that two layers of capacitordielectric films are formed.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Embodiments will be described in detail by referring to the accompanyingdrawings.

(1) First Embodiment

FIGS. 2A to 2L are cross-sectional views showing processes ofmanufacturing a semiconductor device according to a first embodiment.

Firstly, processes for obtaining a cross-sectional structure shown inFIG. 2A will be described.

A groove for STI (shallow trench isolation) for defining an activeregion of a transistor is formed in a surface of a n-type or p-typesilicon (semiconductor) substrate 1. An insulating film, such as siliconoxide, is embedded in the groove to form a device isolation insulatingfilm 3. Note that a device isolation structure is not limited to STI,and the device isolation insulating film 3 may be formed by a LOCOS(local oxidation of silicon) method.

Subsequently, p-type impurities are introduced into the active region ofthe silicon substrate 1 to form a p-well 2. Thereafter, a surface of theactive region is thermally oxidized to form a thermal oxidation filmserving as a gate insulating film 4.

After that, an amorphous or polycrystal silicon film and a tungstensilicide film are sequentially formed on the entire upper surface of thesilicon substrate 1. These films are patterned by photolithography toform two gate electrodes 5.

The above-described two gate electrodes 5 are arranged on the p-well 2so as to be substantially parallel each other with a space therebetween,and these gate electrodes 5 constitute part of a ward line.

Then, n-type impurities are introduced into portions of the siliconsubstrate 1 next to the gate electrodes 5 by ion implantation using thegate electrodes 5 as a mask. Thereby, first and second source/drainextensions 6 a and 6 b are formed.

Thereafter, an insulating film is formed on the entire upper surface ofthe silicon substrate 1, and the insulating film is etched back to beleft beside the gate electrodes 5 as insulating sidewalls 7. As theinsulating film, a silicon oxide film is formed by the CVD method, forexample.

Subsequently, while the insulating sidewalls 7 and the gate electrodes 5are used as a mask, n-type impurities are ion-implanted into the siliconsubstrate 1 again, so that first and second source/drain regions 8 a and8 b are formed beside the two gate electrodes 5 at a distance from eachother.

By the processes so far, first and second MOS transistors TR₁, and TR₂,each of which is constructed from the gate insulating film 4, the gateelectrode 5, and first and second source/drain regions 8 a and 8 b, areformed in the active region of the silicon substrate 1.

Next, after a refractory metal layer, such as a cobalt layer, is formedon the entire upper surface of the silicon substrate 1 by the sputteringmethod, this refractory metal layer is caused to react with silicon byheat. Thereby, a refractory metal silicide film 9 is formed on thesilicon substrate 1. The refractory metal silicide layer 9 is alsoformed on surface portions of the gate electrodes 5, so that theresistance of gate electrodes 5 is lowered.

After that, the refractory metal layer which is left unreacted on thedevice isolation insulating film 3 and the like is removed by wetetching.

Subsequently, a silicon oxynitride (SiON) film is formed with athickness of approximately 200 nm on the entire upper surface of thesilicon substrate 1. The silicon oxynitride film thus formed is used asa cover insulating film 11. After that, a silicon oxide film as a firstinsulating film 12 is formed with a thickness of approximately 1.0 μm onthe cover insulating film 11 by the plasma CVD method using a TEOS gas.

Thereafter, the first insulating film 12 is annealed in a nitrogenatmosphere under an atmospheric pressure at the substrate temperature of700° C. for 30 minutes, so that the first insulating film 12 is madedense. Then, the upper surface of the first insulating film 12 ispolished and planarized by the CMP (chemical mechanical polishing)method.

After that, the cover insulating film 11 and the first insulating film12 are patterned by photolithography to form contact holes on the firstand second source/drain regions 8 a and 8 b. Then, a conductive film isformed on the inner surfaces of the contact holes and the upper surfaceof the first insulating film. The conductive film is then polished bythe CMP method to be left in the contact holes as first and secondconductive plugs 10 a and 10 b. The conductive film is a stacked filmof, for example, a glue film formed by the sputtering method and atungsten film formed by the CVD method. In addition, a film in which atitanium film with a thickness of approximately 20 nm and a titaniumnitride film with a thickness of approximately 50 nm are stacked in thisorder is used for the glue film.

Note that, of the above-described plugs 10 a and 10 b, the secondconductive plug 10 b constitutes a part of a bit line together with thesecond source/drain region 8 b formed thereunder.

Next, as shown in FIG. 2B, a silicon oxynitride film as an oxidationpreventive insulating film 14 is formed by the CVD method with athickness of approximately 100 nm on each of the upper surfaces of theconductive plugs 10 a and 10 b and the first insulating film 12. Thesecond conductive plug 10 b is mainly formed of tungsten, which caneasily be oxidized by oxygen. However, by covering the upper surfacethereof with the oxidation preventive insulating film 14 in this manner,contact defect due to oxidation of the second conductive plug 10 b isprevented even when the plug 10 b is annealed in an oxygen atmosphere.

Then, a silicon oxide film is formed with a thickness of approximately100 nm on the oxidation preventive insulating film 14 by the CVD methodusing the TEOS gas, and is used as an insulating adhesive film 15. Theinsulating adhesive film 15 plays a role to improve adhesiveness withthe lower electrode of a capacitor to be described later.

Next, processes for obtaining a cross-sectional structure show in FIG.2C will be descried.

Firstly, the oxidation preventive insulating film 14 and the insulatingadhesive film 15 are patterned by photolithography to form openings 14 ain these films.

Then, an iridium film is formed with a thickness to completely embed theopenings 14 a, a thickness of 400 nm for example, is formed on theinsulating adhesive film 15 and in the openings 14 a by the sputteringmethod, and is used as an oxygen barrier metal film 16. After that, theexcessive oxygen barrier metal film 16 on the insulating adhesive film15 is polished and removed by the CMP, and the oxygen barrier metal film16 is left only in each of the openings 14 a in an island shape.

The oxygen barrier metal 16 made of iridium is excellent in preventingoxygen permeability, and thus the first conductive plugs 10 a under theoxygen barrier metal 16 are hardly oxidized even if annealing is carriedout in the oxygen atmosphere.

Next, as shown in FIG. 2D, an iridium film is formed with a thickness ofapproximately 150 nm by the DC sputtering method on each of theinsulating adhesive film 15 and the oxygen barrier metal film 16, and isused as a first conductive film 21. Film-forming conditions for this DCsputtering method are not particularly limited. In the presentembodiment, power applied to an iridium target is set to be 0.3 kW, anda flow rate of an argon gas as a sputtering gas is set to 199 sccm. Inaddition, a substrate temperature at the time of forming the firstconductive film 21 is 550° C., and a film-forming time is 350 seconds.

Next, processes for obtaining a cross-sectional structure shown in FIG.2E will be described.

Firstly, the silicon substrate 1 is placed in an unillustrated MOCVDchamber, and the substrate temperature is stabilized at 270° C. Then,DMAH (dimethyl hydride: (CH₃)₂AlH) in the form of liquid in roomtemperature is passed through a vaporizer, which is held at a hightemperature, to be vaporized, and then is supplied into the chambertogether with hydrogen. Here, nitrogen is used as a carrier gas of DHAM,the total pressure in the chamber is set to 1.2 Torr, and the partialpressure of DMAH is set to be 3×10⁻³ Torr.

By maintaining such a state for a predetermined period of time, analuminum crystal layer 20 having the orientation in the (111) directionis grown on the upper surface of the first conductive film 21. As longas the aluminum crystal layer 20 functions as an initial growth nucleusof a PZT film to be formed in the following process, a film thicknessthereof does not need to be thick. Therefore, it is preferable that thealuminum crystal layer 20 be formed with a thickness of 5 nm or less ina dotted pattern as shown in the figure.

In addition, an aluminum material for forming the aluminum crystal layer20 is not limited to the above-described DMAH. In place of DMAH, as analuminum material, diethylaluminum hydride (C₂H₅)₂AlH),triisobutylaluminum (Al(i-C₄H₉)₃), trimethylamine allan (AlH₃N(CH₃)₃),triethylamine allan (AlH₃N(C₂H₅)₃), dimethylethylamine allan (AlH₃N(CH₃)2 (C₂H₅)), an intermolecular compound of DMAH and trimethylaluminum(Al(CH₃)₃), or a compound of these, can also be used.

Next, as shown in FIG. 2F, PZT (Pb(Zr_(x)Ti_(x-1))O₃) (where 0≦x≦1) isformed with a thickness of approximately 120 nm on the aluminum crystallayer 20 by the MOCVD method, and is used as a ferroelectric film 22.Note that in the figure, the dotted lines in the ferroelectric film 22show interfaces of grains of PZT.

Film-forming conditions for the MOCVD method are not limited. In thepresent embodiment, Pb(thd)₂, Zr(DMHD)₄, and Ti(O-iPr) 2 (thd)₂ are usedfor PZT materials, which are supplied to the vaporizer with flow ratesof 0.32 ml per minute, 0.2 ml per minute, and 0.2 ml per minuterespectively, so that the these materials are vaporized at thetemperature of 260° C. After that, the vaporized materials and oxygen of2500 sccm are mixed, and are sprayed onto the silicon substrate 1, whichis maintained at 620° C., under the pressure of 5 Torr for 430 seconds.

At an initial stage of the growth of the ferroelectric film 22, thealuminum crystal layer 20 having the orientation in the (111) directionserves as an initial nucleus to stimulate the growth of theferroelectric film 22 made of PZT. In addition, PZT crystals in theferroelectric film 22 are strongly oriented in the (111) direction dueto the effect of the aluminum crystal layer 20, and accordingly, theferroelectric film 22 shows large spontaneous polarization.

Then, at the time when the growth of the ferroelectric film 22 isfinished, the aluminum crystal layer 20 is taken into the ferroelectricfilm 22. Therefore, the ferroelectric film 22 is made of PZT containingaluminum.

Note that the above-described MOCVD method may be carried out by usingthe MOCVD chamber used for forming the aluminum crystal layer 20, or byusing another chamber.

Although the above-described ferroelectric film 22 is formed by theMOCVD method, the ferroelectric film 22 may be formed by the sputteringmethod or the sol-gel method. In these film forming methods as well, thealuminum crystal layer 20 serves as an initial nucleus of PZT at thetime when the ferroelectric film 22 is grown, and the aluminum crystallayer 20 causes PZT of the ferroelectric film 22 to be easily orientedin the (111) direction.

Note that, when the ferroelectric film 22 is formed by the sputteringmethod, a PZT sputtering target containing at least one of strontium(Sr), calcium (Ca), lanthanum (La), and niobium (Nb) may be used, and aPZT film containing at least one of these elements may be formed as aferroelectric film 22. Among these elements, strontium, calcium, andlanthanum have an effect to enhance spontaneous polarization of theferroelectric film 22. On the other hand, niobium has an effect toreduce a leak current of the ferroelectric film 22.

Furthermore, when the ferroelectric film 22 is formed by the sputteringmethod, rapid thermal annealing is performed for the ferroelectric film22 in an atmosphere containing oxygen at a substrate temperature of 500°C. to 750° C. so as to crystallize the ferroelectric film 22. At thistime, the aluminum crystal layer 20 formed earlier plays a role as aninitial nucleus to grow PZT crystals with excellent controllability sothat the crystals are oriented in the (111) direction.

Next, as shown in FIG. 2G, an iridium oxide film is formed as a secondconductive film 22 with a thickness of approximately 200 nm on theferroelectric film 22 by the sputtering method. Here, a platinum filmmay be formed as the second conductive film 23, in place of the iridiumoxide film.

Next, as shown in FIG. 2H, after an unillustrated hard mask is formed onthe second conductive film 23, the second conductive film 23, theferroelectric film 22, and the first conductive film 21 are subjected tothe plasma etching in an atmosphere containing a halogen element, sothat these films 21-23 are simultaneously etched with the sputteringreaction. Thereby, capacitors Q, each of which is formed by stacking alower electrode 21 a, a capacitor dielectric film 22 a, and an upperelectrode 23 a in this order, are formed. Thereafter, the hard mask isremoved.

The lower electrodes 21 a of the capacitors Q are each electricallyconnected to the corresponding first source/drain regions 8 a throughthe corresponding oxygen barrier metal film 16 and the correspondingfirst conductive plug 10 a. In addition, in the etching performed forforming the capacitors Q, the insulating adhesive film 15 made ofsilicon oxide functions as an etching stopper, and thus the secondconductive plug 10 b remains protected by the insulating adhesive film15 and the oxygen preventive insulating film 14.

After that, in order to recover damages received in the capacitordielectric film 22 a due to the above plasma etching, annealing iscarried out for the capacitor dielectric film 22 a in a furnacecontaining oxygen under conditions with the substrate temperature of650° C. and the processing time of 60 minutes. Such annealing is alsocalled recovery annealing.

At the time of this recovery annealing, the second conductive plug 10 bconstituting the bit line is protected by the oxidation preventiveinsulating film 14 formed thereon from being oxidized. On the otherhand, the first conductive plugs 16 directly under the capacitors Q areprotected by the oxygen barrier metal film 16 from being oxidized.

Next, as shown in FIG. 2I, a PZT film as a capacitor protectiveinsulating film 25 is formed with a thickness of approximately 50 nm onthe capacitors Q by the sputtering method. This capacitor protectiveinsulating film 25 is used to protect the capacitors Q from a reducingatmosphere such as hydrogen, and may be made of an alumina film insteadof the PZT film.

After that, the capacitors Q are annealed in the furnace under acondition with the substrate temperature of 650° C. for approximately 20minutes.

Subsequently, a silicon oxide film as a second insulating film is formedon the capacitor protective insulating film 25 by the HDPCVD (highdensity plasma CVD) method using a silane gas as a reaction gas. Then,the upper surface of the second insulating film 26 is polished andplanarized by the CMP method, so that the thickness of the secondinsulating film 26 on the upper electrode 23 a becomes approximately 300nm.

Next, as shown in FIG. 2J, films from the second insulating film 26through the oxidation preventive insulating film 14 are etched byphotolithography, and a first hole 26 a is formed in these films. Then,a titanium film and a titanium nitride film are formed in this order onthe inner surface of the first hole 26 a and the upper surface of thesecond insulating film 26 by the sputtering method, and the films areused as a glue film. Furthermore, the tungsten film is formed on theglue film by the CVD method, and the first hole 26 a is completelyembedded by this tungsten film. Thereafter, the excessive tungsten filmand glue film on the second insulating film 26 are polished and removed,so that these films are left in the first hole 26 a as a thirdconductive plug 27.

Next, as shown in FIG. 2K, a silicon oxynitride film as an oxidationprotective film 28 is formed with a thickness of approximately 100 nm oneach of the upper surfaces of the third conductive plug 27 and thesecond insulating film 26 by the CVD method.

Then, films from the oxidation preventive film 28 through the capacitorprotective insulating film 25 are patterned by photolithography to fromsecond holes 26 b in the second insulating film 26 on the upperelectrodes 23 a. The capacitors Q receiving damages by forming thesecond holes 26 b are recovered by annealing. The annealing is carriedout, for example, in an atmosphere containing oxygen at the substratetemperature of 550° C. for approximately 60 minutes.

By forming the oxidation preventive film 28 before the annealing asdescribed above, contact defect due to oxidation of the third conductiveplug 27 in the annealing can be prevented.

Then, the oxidation preventive film 28 is removed by etch-back after theannealing is finished.

Next, processes for obtaining a cross-sectional structure shown in FIG.2L will be described.

Firstly, a multi-layered metal film is formed on inner surfaces of thesecond holes 26 b and the upper surface of the second insulating film26. As the multi-layered metal film, a titanium film with a thickness ofapproximately 60 nm, a titanium nitride film with a thickness ofapproximately 30 nm, a copper-containing aluminum film with a thicknessof approximately 400 nm, a titanium film with a thickness ofapproximately 5 nm, and a titanium nitride film with a thickness of 70nm are formed in this order, for example.

After that, the multi-layered metal film is patterned byphotolithography, so that first layer metal wirings 29 a, which areelectrically connected to the upper electrodes 23 a through the secondholes 26 b, and a conductive pad 29 b, which is electrically connectedto the third conductive plug 27, are formed.

With this, the basic structure of the semiconductor device according tothe present embodiment is completed.

According to the present embodiment described above, as described inFIG. 2F, the aluminum crystal layer 20 is formed on the first conductivefilm 21. Therefore, the ferroelectric film 22 made of PZT is grown whileusing the aluminum crystal layer 20 as the initial nucleus, and the(111) orientation of PZT is induced by the aluminum crystal layer 20having the orientation in the (111) direction.

Thus, unlike the conventional method, there is no need that a titaniumfilm for forming an initial nucleus made of titanium oxide is used forthe lower electrodes 21 a. In addition, when compared with theconventional method in which an initial nucleus of titanium oxide isformed by utilizing diffusion of titanium, the aluminum crystal layer 20to be an initial nucleus of PZT is surely formed on the lower electrodes21 a. Accordingly, the orientation of the ferroelectric film 22 can besurely enhanced due to the initial nucleus.

As a result, the capacitor dielectric film 22 a with an orientationaligned on the lower electrodes 21 a can be formed by the effect of thealuminum crystal layer 20 in the present embodiment even when an iridiumfilm, on which it has conventionally been difficult to form a PZT filmwith a good orientation, is formed as lower electrodes 21 a.

Furthermore, since the ferroelectric film 20 is formed by the MOCVDmethod, the orientation the ferroelectric film 22 can be enhanced by thealuminum crystal layer as described above, while the crystals of theferroelectric film 22 are caused to be highly dense to enableminiaturization of the capacitors Q.

Note that when the lattice constant of the initial nucleus comes closerto that of the PZT (111), the ferroelectric film 22 can be oriented inthe (111) direction more precisely, and accordingly, the spontaneouspolarization of the ferroelectric film 22 becomes larger.

FIG. 3 is a graph obtained by investigating a lattice spacing differencein relation to the PZT (111) for various crystals. Note that the latticespacing difference is defined as “(lattice spacing of PZT (111)—latticespacing of crystals of a comparison target)/lattice spacing of PZT(111).”

An Al (111) crystal constituting the aluminum crystal layer 20 is acrystal cubic, and lattice spacing thereof is 2.34. In contrast, a PZT(111) crystal is also a crystal cubic, and lattice spacing thereof is2.34, which is the same as that of the Al (111) crystal. Hence, thedifference in the lattice spacing of Al (111) and PZT (111) is 0 asshown in FIG. 8. Thus, the ferroelectric film 22 made of PZT is easilylattice-matched with the aluminum crystal layer 20, so that theferroelectric film 22 having reduced orientation disorder due to latticemismatch can be formed on the aluminum crystal layer 20.

In contrast, Pt (111) conventionally used as a lower electrode forinducing the (111) orientation of PZT has lattice spacing of 2.26. Thus,Pt (111) is difficult to be lattice-matched with the PZT (111) havingthe lattice spacing of 2.34. In addition, PbTiO₃ (111) and TiO₂ (200),each of which is conventionally formed as an initial nucleus of PZT,have both lattice spacing of 2.30. Thus, PbTiO₃ (111) and TiO₂ (200) arealso difficult to be lattice-matched with the PZT (111).

In this manner, the aluminum crystal layer 20 made of Al (111) islattice-matched with the ferroelectric film 20 very easily, whencompared with other crystals. As a result, it becomes possible thatdefects due to lattice mismatch are hardly caused in the ferroelectricfilm 22.

The aluminum crystal layer 20 is excellent in effects of increasing theorientation of the ferroelectric film 22 made of PZT as descried above.However, if the thickness of the aluminum crystal layer 20 is too thick,aluminum taken into the ferroelectric film 22 becomes Al₂O₃. As aresult, ferroelectric characteristics of the ferroelectric film 22, suchas residual polarization charges, are deteriorated. In order to avoidsuch inconvenience, it is preferable that the film thickness of thealuminum crystal layer 20 be set to as thin as possible, for example, 5nm or less. If the aluminum crystal layer 20 is formed with a thicknessthicker than 5 nm, the ferroelectric characteristics of theferroelectric film 22 are deteriorated from the reason described above,and the ferroelectric film 22 does not show the ferroelectriccharacteristics.

(2) Second Embodiment

FIGS. 4A to 4J are cross-sectional views showing processes ofmanufacturing a semiconductor device according to a second embodiment.Note that components described in the first embodiment are provided withthe same reference numerals as those in the first embodiment, and thedescription thereof will be omitted.

In order to manufacture a semiconductor device according to the presentembodiment, the process described in FIG. 2A in the first embodiment isfirstly carried out. Thereafter, as shown in FIG. 4A, an iridium film asa first conductive film 21 is formed with a thickness of approximately200 nm on each of the upper surfaces of first and second conductiveplugs 10 a and 10 b as well as the upper surface of a first insulatingfilm 12, by a DC sputtering method.

Next, as shown in FIG. 4B, this first conductive film 21 is patterned byphotolithography to form a lower electrode 21 a in an island shape oneach of the first conductive plugs 10 a.

Subsequently, as shown in FIG. 4C, an aluminum crystal layer 20 in adotted pattern is formed with a thickness of 5 nm or less on sidesurfaces and the upper surfaces of lower electrodes 21 a and the uppersurface of a first insulating film 11, by the MOCVD method employing thesame film-forming conditions as those of the first embodiment.

Thereafter, as shown in FIG. 4D, a PZT film is formed with a thicknessof approximately 120 nm on the aluminum crystal layer 20 and the firstinsulating film 12 by the MOCVD method. The PZT film thus formed is usedas a ferroelectric film 22. Film-forming conditions of the ferroelectricfilm 22 are same as those of the first embodiment, and thus thedescription thereof will be omitted.

Next, as shown in FIG. 4E, an iridium oxide film is formed on theferroelectric film 22 by the sputtering method as a second conductivefilm 23. Here, a thickness of the second conductive film 23 is notparticularly limited. In the present embodiment, the thickness is set toapproximately 200 nm.

Subsequently, as shown in FIG. 4F, the second conductive film 23 and theferroelectric film 22 are simultaneously patterned by photolithography.Thus, the ferroelectric film 22 is left on the side surfaces and theupper surfaces of the lower electrodes 21 a as capacitor dielectricfilms 22 a. Furthermore, the second conductive film 23 is left over andbeside the lower electrodes 21 a as upper electrodes 23 a.

With this, capacitors Q, each of which is formed by stacking the lowerelectrode 21 a, the capacitor dielectric film 22 a, and the upperelectrode 23 a in this order on the first conductive plug 10 a, areformed.

Next, as shown in FIG. 4G, in order to protect the capacitors Q from areducing atmosphere such as hydrogen, a PZT film as a capacitorprotective insulating film 25 is formed with a thickness ofapproximately 50 nm on each of the capacitors Q, by the sputteringmethod.

Subsequently, a silicon oxide film is formed on the capacitor protectiveinsulating film 25 by the HDPCVD method using a silane gas as a reactiongas, and the silicon oxide film is used a second insulating film 26.Thereafter, the upper surface of the second insulating film 26 ispolished and planarized by the CMP method. Thus, the thickness of thesecond insulating film 26 becomes approximately 300 nm on the upperelectrode 23 a.

Next, as shown in FIG. 4H, the second insulating film 26 and thecapacitor protective insulating film 25 are patterned byphotolithography, and a first hole 26 a is formed in these films on thesecond conductive plug 10 b. Thereafter, by carrying out a processsimilar to that described in FIG. 2J of the first embodiment, a thirdconductive plug 27 is formed in the first hole 26 a. Note that the thirdconductive plug 27 is constructed by forming the glue film, such as atitanium nitride film, and tungsten film in this order.

Next, as shown in FIG. 4I, a silicon oxynitride film as an oxidationpreventive film 28 is formed with a thickness of 100 nm on each of theupper surfaces of the third conductive plug 27 and the second insulatingfilm 26 by the CVD method.

Then, films from the oxidation preventive film 28 through the capacitorprotective insulating film 25 are patterned by photolithography to forma second hole 26 b in the second insulating film 26 on the upperelectrode 23 a.

Thereafter, in order to recover damages received in the capacitors Qwhen the second hole 26 a is formed, annealing is carried out for thecapacitors Q in an atmosphere containing oxygen at a substratetemperature of 550° C. for approximately 60 minutes.

During this annealing, the third conductive plug 27 is protected fromthe atmosphere containing oxygen by the oxidation preventive film 28.Thus, contact defect due to oxidation of the third conductive plug 27can be prevented.

Thereafter, the oxidation preventive film 28 is removed by etch-back.

Next, as shown in FIG. 4J, a multi-layered metal film is formed in thesecond hole 26 b and on the second insulating film 26 by the sputteringmethod. This multi-layered metal film is patterned to form first layermetal wirings 29 a and a conductive pad 29 b. Similar to the firstembodiment, the multi-layered metal film is formed by stacking atitanium film with a thickness of approximately 60 nm, a titaniumnitride film with a thickness of approximately 30 nm, acopper-containing aluminum film with a thickness of approximately 400nm, a titanium film with a thickness of approximately 5 nm, and atitanium nitride film with a thickness of approximately 70 nm in thisorder.

With this, the basic structure of the semiconductor device according tothe present embodiment is completed.

In the capacitors Q of this semiconductor device, a capacitor dielectricfilm 22 a is formed not only on the upper surface of the lower electrode21 a but also on side surfaces of the lower electrode 21 a, as shown inFIG. 4J. As a result, when compared with the first embodiment, a facingarea of the lower electrode 21 a and the capacitor dielectric film 22 aincreases. Thus, the amount of residual polarization charges in onecapacitor Q can be increased. Such a structure of the capacitor Q willbe hereinafter referred to as a three dimensional capacitor structure.

In the three dimensional capacitor structure, as shown in FIG. 4D, it isnecessary that the ferroelectric film 22 is formed on side surfaces 21 cof each of the lower electrodes 21 a. If step coverage of thisferroelectric film 22 is poor, the thickness of the ferroelectric film22 becomes small at a corner 21 b of the lower electrode 21 a, and leakcurrent flows at the corner 21 b from the lower electrode 21 a to theupper electrode 23 a (see, FIG. 4J).

Hence, in the three dimensional capacitor structure, the ferroelectricfilm 22 is required to have preferable step coverage.

In view of such a problem, the ferroelectric film 22 is formed by theMOCVD method with which a film excellent in step coverage can be formedin the present embodiment. Thus, the thickness of the ferroelectric film22 is substantially same on the side surfaces and the upper surface ofthe lower electrode 21 a. Consequently, the leak current between theupper electrode 23 a and the lower electrode 21 a described above can besuppressed, and the capacitor Q with high quality can be formed.

In addition, as shown in FIG. 4D, the aluminum crystal layer 20 servingas a growth nucleus of the PZT is formed on the lower electrode 21 a.Thus, as described in the first embodiment, PZT in the ferroelectricfilm 22 can be strongly oriented in the (111) direction.

(3) Third Embodiment

In the above-described first and second embodiments, a capacitordielectric film 22 a is made of a single layer of a PZT film. However,the present embodiment is not limited to this.

For example, as shown in FIG. 5, a stacked film of a first ferroelectricfilm 22 b made of PZT and a second ferroelectric film 22 c made of PZTinto which at least one of strontium, calcium, lanthanum, and niobium isdoped may be formed as the capacitor dielectric film 22 a in the firstembodiment.

As shown in FIG. 6, such a stacked film of the first and secondferroelectric films 22 b and 22 c may be formed also as the capacitordielectric film 22 a in the second embodiment.

Even when the capacitor dielectric film 22 a with a stacked structureshown in FIGS. 5 and 6 is employed, the orientation of PZT (111) isinduced in each of the films 22 b and 22 c due to the effect of thealuminum crystal layer 20, as is described in the first and secondembodiments, so that the capacitor dielectric film 22 a can be extremelywell oriented.

In addition, in the above-described first and second embodiments, thedescriptions have been given to a stack-type FeRAM in which a lowerelectrode 21 a is formed over a first conductive plug 10 a, but thepresent embodiments may be applied also to a planar-type FeRAM.

The foregoing is considered as illustrative only of the principles ofthe present invention. Further, since numerous modifications and changeswill readily occur to those skilled in the art, it is not desired tolimit the invention to the exact construction and applications shown anddescribed, and accordingly, all suitable modifications and equivalentsmay be regarded as falling within the scope of the invention in theappended claims and their equivalents.

1. A method for manufacturing a semiconductor device, comprising:forming an insulating film over a semiconductor substrate; forming afirst conductive film over the insulating film; forming an aluminumcrystal layer on the first conductive film; forming a ferroelectric filmcontaining Pb(Zr_(x)Ti_(1-x))O₃ (where 0≦x≦1) on the aluminum crystallayer; forming a second conductive film on the ferroelectric film; andpatterning the first conductive film, the ferroelectric film, and thesecond conductive film to form a capacitor including a lower electrode,a capacitor dielectric film, an upper electrode which are sequentiallystacked, wherein the aluminum crystal layer is formed in a dottedpattern.
 2. The method for manufacturing a semiconductor deviceaccording to claim 1, wherein the orientation of the aluminum crystallayer is in a (111) direction.
 3. The method for manufacturing asemiconductor device according to claim 1, wherein the aluminum crystallayer is formed with a thickness of 5 nm or less.
 4. The method formanufacturing a semiconductor device according to claim 1, wherein theferroelectric film is formed by an MOCVD (metal organic CVD) method. 5.The method for manufacturing a semiconductor device according to claim1, wherein an iridium film is formed as the first conductive film. 6.The method for manufacturing a semiconductor device according to claim1, wherein a film in which at least one of strontium, calcium,lanthanum, and niobium is contained in the Pb(Zr_(x)Ti_(1-x))O₃ isformed as the ferroelectric film.
 7. The method for manufacturing asemiconductor device according to claim 1, wherein a stacked film of afirst ferroelectric film made of Pb(Zr_(x)Ti_(1-x))O₃ and a secondferroelectric film in which at least one of strontium, calcium,lanthanum, and niobium is contained in Pb(Zr_(x)Ti_(1-x))O₃ is formed asthe ferroelectric film.
 8. The method of manufacturing a semiconductordevice according to claim 1, wherein the first conductive film is formedby a DC sputtering method.
 9. A method for manufacturing a semiconductordevice, comprising: forming an insulating film over a semiconductorsubstrate; forming a first conductive film over the insulating film;patterning the first conductive film to form a lower electrode; formingan aluminum crystal layer on a side surface and an upper surface of thelower electrode; forming a ferroelectric film containingPb(Zr_(x)Ti_(1-x))O₃ (where 0≦x≦1) on the aluminum crystal layer and theinsulating film; forming a second conductive film on the ferroelectricfilm; patterning the ferroelectric film to leave the ferroelectric filmas a capacitor dielectric film on the side surface and the upper surfaceof the lower electrode; and patterning the second conductive film toleave the second conductive film, as an upper electrode, over and besidea side of the lower electrode, and forming a capacitor with the upperelectrode, the capacitor dielectric film, and the lower electrode. 10.The method for manufacturing a semiconductor device according to claim9, wherein an orientation of the aluminum crystal layer is in a (111)direction.
 11. A semiconductor device comprising: a semiconductorsubstrate; an insulating film formed over the semiconductor substrate;and a capacitor, which is formed on the insulating film, and which isformed by sequentially stacking a lower electrode, a capacitordielectric film containing Pb(Zr_(x)Ti_(1-x))O₃ (where 0≦x≦1) andaluminum, and an upper electrode.
 12. The semiconductor device accordingto claim 11, wherein the lower electrode is made of iridium.